`timescale 1ns/1ns
module tb_cm0 ();

    reg clk;
    reg nRst;

    initial begin
        clk <= 1'b0;
        nRst <= 1'b0;
        #100;
        nRst <= 1'b1;
    end

    always #10 clk <= ~clk;
    wire tessss;
    assign tessss = clk;

    cortex_m0 test(
        .XTAL1          (tessss),
        .NRST           (nRst) 
    );
    
endmodule